1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a reset function.
2. Description of Related Art
Some semiconductor devices such as DRAM (Dynamic Random Access Memory) performs a reset operation of an internal circuit thereof when a reset signal is activated. For example, when a power supply is turned on from the outside, a power-on reset signal is generated by a power-on reset circuit, so that each internal circuit inside a semiconductor device is reset. Each internal circuit is initialized by the reset operation thereby the semiconductor device typically enters an operable state.
The reset signal includes an external reset signal in addition to the power-on reset signal. The external reset signal is issued when the system needs to be initialized. When the external reset signal is activated, the semiconductor device is forcibly reset.
When receiving the reset signal, the semiconductor device such as DDR3 (Double Data Rate 3) type SDRAM (Synchronous Dynamic Random Access Memory) first transits to a “reset state” to stabilize an internal voltage. After a predetermined time (which will be called “reset time” below) has elapsed, the semiconductor device transits to an “initial state” to be initialized (see Japanese Patent Application Laid-Open No. 2007-95278).
In the reset state, the semiconductor device increases or reduces an external voltage thereby to generate the internal voltage having a predetermined designed value.
However, the inventor recognized that the internal voltage may become higher than the designed value at the transition to the initial state. If the internal voltage remains higher than the designed value, the initialization processing cannot be properly performed.